Synplicity Enhances Synplify Pro Software

Supports Verilog-2001 Standard

Synthesis Solution Offers Improved Performance and Support for New Operating Systems and Devices

SUNNYVALE, Calif.--(BUSINESS WIRE)--April 8, 2002--Synplicity, Inc. (Nasdaq:SYNP - news), a leading supplier of software for the design and verification of semiconductors, today announced it has enhanced its market-share leading programmable logic device (PLD) synthesis software, Synplify Pro®. The Synplify Pro software now includes support for the Verilog-2001 standard and offers support for new devices and new operating systems (OSs). The latest version of the Synplify Pro software also includes several quality of results (QoR) improvements and enhancements to its incremental timing engine and automated register re-timing feature, providing designers with added productivity and performance-improving benefits.

"We believe our Synplify Pro software continues to raise the bar for synthesis products by providing timely support for important new standards and offering the best quality of results for device families such as Altera's Stratix and Xilinx Virtex-II Pro," said Andy Haines, vice president of marketing at Synplicity. "Support for the Verilog-2001 standard within the Synplify Pro software enables our customers to utilize the numerous benefits provided by the design language. With the additional new device support, OS support and its QoR enhancements, we believe the Synplify Pro software is an ideal choice for designers of highly complex designs who need to achieve the highest level of performance quickly."

Market-Share Leading PLD Synthesis Software Offers Support for Verilog-2001 Standard

The latest version of the Synplify Pro software supports the new Verilog-2001 standard, an enhanced version of the Verilog design language. The Verilog-2001 standard offers many significant new features including greater support for configurable intellectual property (IP) modeling, deep-submicron accuracy and design management. With the new Synplify Pro software, customers can take advantage of powerful new features in Verilog-2001 such as 'generate' and signed arithmetic expressions, which may be applied to registers, nets, function returns and literals. Other Verilog-2001 features supported in the Synplify Pro software include: exponent power operator, comma-separated sensitivity list, combinatorial logic sensitivity, automatic width extension past 32 bits and ANSI-style port lists.

Behavior Extracting Synthesis Technology® Algorithms Infer Designer Intent

Driven by the proprietary Behavior Extracting Synthesis Technology (B.E.S.T.(TM)) algorithms, Synplicity's synthesis solutions can deliver optimal circuit performance with the most efficient area utilization. The Synplify product's B.E.S.T. technology extracts designer intent from HDL code by inferring complex memories, finite state machines (FSMs) and advanced mathematical functions then efficiently maps them to device-specific hardware resources. Additionally, with this new release, Synplicity has built upon its fast, incremental timing analysis engine and automated register re-timing feature. The high-capacity timing analysis engine makes timing estimations even more accurate, producing highly optimized circuits with fewer design iterations. With automatic re-timing, the Synplify Pro software eliminates the labor-intensive process of analyzing critical paths and changing HDL code to balance delay and can automatically reposition registers within combinatorial logic to balance routing and ultimately improve circuit performance.

Synplicity has advanced its support in the Synplify Pro software for Altera's Stratix device family enabling rapid and efficient implementation using specialized optimizations to take advantage of the dedicated Multiply Accumulate (MAC) functions and TriMatrix Memory blocks in these high-performance devices.

The software features several QoR improvements for Xilinx's Virtex, VirtexE and Virtex II devices, including auto mapping of ROMs to BlockRAMs and pipelined block multiplier support. These QoR improvements enable designers to increase device performance while improving the utilization of dedicated chip resources, resulting in reduced implementation.

The Synplify Pro software also offers new device support for Actel's ProASIC Plus, Lattice's ispGDX2 and isp5000MX, and Xilinx's CoolRunner II and Virtex-II Pro FPGA families.

Pricing and Availability

The Synplify® 7.1 and Synplify Pro 7.1 synthesis solutions are available now. Pricing for the Synplify software starts at $9,000 (U.S.) and pricing for Synplify Pro software starts at $19,000 (U.S.). Current customers on maintenance will be upgraded at no additional cost. The Synplify and Synplify Pro solutions are also available for Windows XP and Linux (RedHat 7.2) operating systems.

About Synplicity

Synplicity, Inc. (Nasdaq: SYNP - news) is a leading provider of software products that enable the rapid and effective design and verification of semiconductors used in networking and communications, computer and peripheral, consumer and military/aerospace electronics systems. Recognizing the company's industry-leading position, Dataquest named Synplicity as the #1 provider of PLD synthesis tools in 2000 with a 45 percent market share. Synplicity leverages its innovative logic synthesis, physical synthesis and verification software solutions to improve performance and shorten development time for complex programmable logic devices, application specific integrated circuits (ASICs) and system-on-chip (SoC) integrated circuits. The company's fast, easy-to-use products offer high quality of results, support industry-standard design languages (VHDL and Verilog) and run on popular platforms. As of December 31, 2001, Synplicity employed 266 people in its 20 facilities worldwide. Synplicity is headquartered in Sunnyvale, Calif. For more information on Synplicity, visit http://www.synplicity.com.

The specific features, functionality and release timing of any new versions of current products as described in this press release remain at the sole discretion of Synplicity, Inc., and Synplicity does not make any warranty as to when or if such specific features, functionality or releases may occur.

Note to Editors: Synplicity, Behavior Extracting Synthesis Technology, Synplify and Synplify Pro are registered trademarks of Synplicity, Inc. B.E.S.T. is a trademark of Synplicity, Inc. All other brands or products are the trademarks or registered trademarks of their respective owners. SYB-156

     Synplicity, Inc.
     Jeff Garrison, 408/215-6000 (Reader Contact)
     jeff@synplicity.com
         or
     Porter Novelli
     Steve Gabriel, 408/369-1500 (PR Contact)
     steve.gabriel@porternovelli.com